1. Field
The present disclosure generally relates to integrated circuits (ICs). More specifically, the present disclosure relates to integrating through substrate vias (TSVs) created from a wafer backside into advanced CMOS (complementary metal oxide semiconductor) nodes.
2. Background
The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle of line (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate contact formation. Middle of line layers may include, but are not limited to, MOL contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.
A TSV (through substrate via) is generally used to access active devices on a front side of an integrated circuit (IC) device. The TSV co-exists at the same level as MOL components (e.g., MOL contacts and vias). TSV fabrication, however, presents various challenges with node size scaling below forty-five (45) nanometers (nm). MOL device features are on the order of ten (10) nanometers (nm); however, the TSV is on the order of micrometers (ums). Consequently, a small variation in the TSV fabrication process may damage the MOL devices.